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EDK Overview Dr.K Embedded Development Kit • What is Embedded Development Kit (EDK)? – The Embedded Development Kit is the Xilinx software suite for designing complete embedded programmable systems – The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC™ hard processor cores, and/or Xilinx MicroBlaze™ soft processor cores – It enables the integration of both hardware and software components of an embedded system Where to get EDK? • $495 to buy (from www.avnet.com, www.nuhorizons.com) • 30-day evaluation is available (www.xilinx.com/ise_eval/index.htm) • EDK Manuals & Application Notes (www.xilinx.com/ise/embedded/edk_pstudio.htm) Current Technologies for Embedded Systems • • • • Microcontroller-based systems DSP processor-based systems ASIC technology FPGA technology Embedded Design in an FPGA • Embedded design in an FPGA consists of the following: – Develop FPGA hardware design – Generate drivers and libraries – Create the software application • Software routines • Interrupt service routines (optional) • Operating System (OS) or Real Time Operating System (RTOS) (optional) MicroBlaze Processor-Based Embedded Design BRAM Local Memory Bus MicroBlaze 32-Bit RISC Core I-Cache BRAM D-Cache BRAM Configurable Sizes Flexible Soft IP Arbiter Processor Local Bus Bus Bridge On-Chip Peripheral Bus Custom Functions Custom Functions CacheLink 10/100 E-Net Memory Controller UART GPIO On-Chip Peripheral Off-Chip Memory SDRAM FLASH/SRAM This is a v7.1 architecture. Versions 6.0 or earlier do not support PLB bus off the processor. Instead they have OPB bus Arbiter Fast Simplex Link 0,1….15 PLB OPB Microblaze Processor ; Load the value 0x70000000 ; into register r5 XOR r5, r5, r5 ORI r5, r5, 0x7000000 • MicroBlaze is a 32-bit RISC processor modeled on DLXi (see Henessy and Patterson's book). • Soft-configurable (many options like cache, FPU) • Contains 32 general purpose registers (R0…R31) • Single-issue 3-5 stage pipelined processor which operates on 32bit instructions with 3 operands and 2 addressing modes. IP Cores See IP Catalog or Xilinx web for Complete Listing of free and evaluation IP Cores • Open-source cores are available at www.opencores.org • Xilinx has created a wide variety of IP cores: – Bus infrastructure cores • Busses: PLB, OPB • Bridges: PLB2OPB , OPB2PLB • 10/100 Ethernet MAC, CAN controller, HDLC Interface, Flexray, MOST, USB2 • Serial Peripheral Interface, IIC Interface, UART 16550, UART lite • Fixed interval timer, watchdog timer, central DMA controller • Block RAM, DDR/DDR2/SDRAM (multi-port available), SRAM/Flash (multi-port available), Compact Flash • General Purpose I/O (GPIO) • Mailbox, MUTEX – Communication: High-Speed – Communication: Low-Speed – DMA and Counter – Memory Controllers for – General Purpose I/O – Interprocessor Communication Memory Mapped I/O • A single set of instructions used to access memory and all peripherals. • Memory access latency is 5 clock cycles (typical). • Peripheral access latency is 50 clock cycles (empty bus). What is unique about FPGA EDK? ANSWER: Fast Simplex Links I-Cache BRAM D-Cache BRAM BRAM Local Memory Bus MicroBlaze 32-Bit RISC Core Configurable Sizes Arbiter Processor Local Bus Bus Bridge On-Chip Peripheral Bus Custom Functions Custom Functions CacheLink 10/100 E-Net Memory Controller UART GPIO On-Chip Peripheral SDRAM Off-Chip FLASH/SRAM Memory Arbiter Fast Simplex Link 0,1….15 PLB OPB Fast Simplex Links ( FSL) • • • • Unidirectional point-to-point FIFO-based communication Dedicated (unshared) and nonarbitrated architecture Dedicated MicroBlaze™ C and ASM instructions for easy access High speed, access in as little as two clocks on processor side, 600 MHz at hardware interface • Available in Xilinx Platform Studio (XPS) as a bus interface library core from Hardware → Create or Import Peripheral Wizard FSL_M_Clk FSL_M_Control FSL_M_Write FSL_M_Full FIFO Depth FIFO 32-bit data FSL_S_Clk FSL_M_Data [0:31] FSL_S_Data [0:31] FSL_S_Control FSL_S_Read FSL_S_Exists Embedded Development Tool Flow Overview C Code VHDL or Verilog Standard Embedded SW Development Flow Embedded Development Kit Standard FPGA HW Development Flow Code Entry Include the BSP C/C++ Cross Compiler and Compile the Software Image Linker Board Support Package Data2MEM HDL Entry System Netlist Instantiate the Simulation/Synthesis ‘System Netlist’ and Implement Implementation the FPGA ? Load Software Into FLASH 2 Compiled ELF 3 Compiled BIT 1 ? Download Combined Image to FPGA Download Bitstream Into FPGA Debugger Chipscope RTOS, Board Support Package Embedded Design Flow • Develop the embedded hardware – Quickly create a system targeting a board using Base System Builder Wizard – Extend the hardware system • Add peripherals from the IP Catalog • Create and add a custom peripheral using the Create/Import Peripherals Wizard • Insert ChipScope™ Pro cores into the system using the Debug Configuration Wizard – Generate HDL netlists using PlatGen – Perform an HDL simulation using an HDL simulator • Generate simulation models using SimGen • Develop the embedded software – Generate libraries and drivers with LibGen – Create and debug the software ap in XPS or the Software Development Kit (SDK) • Compile using the GNU C/C++ compiler (gcc) • Connect to the target using Xilinx Microprocessor Debug (XMD) • Debug using the GNU debugger (gdb) • Operate in hardware – Generate the bitstream and configure the FPGA – Initialize external flash memory • The bitstream initializer (BitInit) will update FPGA instruction memory with the executable • Write to external flash using the Flash Writer utility • Generate an external compact flash configuration file using the System ACE File generator (GenACE) Demo Time • • • • • • Start a New Project Select Microprocessor Select Peripherals Setup Software Download bit file to FPGA Finish up!